There is a continuing trend towards increasing the capacity of DRAMs. Such an increase in capacity is best achieved by decreasing the surface area of the memory cells and increasing their packing density to increase the size of the array in the silicon chip that houses the DRAM.
Various techniques have been used to increase the packing density. One technique has been to use a vertical trench to form the capacitor that serves as the storage site of the cell.
Another technique has been to use as the switch transistor a vertical transistor formed on a sidewall of the vertical trench that provides the capacitor. Another technique has been to use a common drain and common bit line for a pair of switch transistors formed in a single active area that includes a pair of memory cells. Another technique is to form the storage capacitor of the cell as a stack of layers on the surface of the silicon chip. Other techniques have involved particular shapes and layouts for the active area of the cell to permit more efficient packing.